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The deployment of converged networks for triple-play, IPTV and advanced VPN business services presents service providers with a significant opportunity to generate new revenue streams. Yet it also presents a major challenge in delivering high bandwidth, packet-based services over a converged infrastructure without compromising on quality of service. The problem is further compounded by the fact that that the take-rate and bandwidth requirements for new IP-based services are difficult to predict. Systems OEMs need to build products that can "pay as you grow". Scalable architectures are crucial to meet the diverse quality of service needs demanded by current and future services the service providers' networks will have to support.

Finally, these increasingly complex, scalable platforms must be designed inside ever-decreasing development cycles. Customers are therefore now looking at all aspects of a system's architecture and making decisions as to where to focus their engineering resources in order to deliver compelling, differentiated platforms to the market.

As the diagram below indicates, Enigma's strategy is to meet this system challenge by delivering solutions that combine the strengths of Enigma's HybriCore switches and fabric managers with the fine-grained QoS capabilities of discrete traffic manager and network processor components. Enigma is working with a number of semiconductor partners such as TPACK and EZchip that develop such devices to prove component interoperability and, more importantly, to develop platforms that demonstrate the QoS capabilities and scalability of the combined devices.

  • For more information on the Enigma/TPACK solution, please see the white paper and datasheet.
  • For more information on the Enigma/EZchip NP-2 NPU solution, please see the interoperability test report.

    The Enigma HybriCore Solution

    Inside this type of architecture, the role of the HybriCore chipset is to provide high performance, regulated, traffic manager to traffic manager channels that can be utilized by the traffic manager devices themselves. The HybriCore chipset provides a significant amount of performance headroom to ensure that customers can "future-proof" their systems, and addresses the system challenge outlined above in three ways:

    • Performance: As the highest performance, densest chipset on the market, it provides significant performance headroom to prolong the viability of deployed systems.
    • Flexibility: The range of fabric managers and the capability of the backplane serial links to operate across a broad spectrum of frequencies allows companies to develop sophisticated functionality upgrade strategies while leveraging the core switching architecture that is initially deployed into the field. Additionally, the system approach outlined above allows different combinations of traffic manager/NPU subsystems and line card densities to be mixed inside a system.
    • Density: The family of fabric managers, which includes the industry's first 40 Gbps, full duplex component, deliver unprecedented levels of integration. The fabric manager requires no external buffer memory, which simplifies line card design, reduces system power and cost and enables system designers to finally contemplate the development of 80 Gbps+ line cards using off-the-shelf silicon.

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